This invention relates to asynchronous data networks, such as asynchronous transfer mode (ATM) networks, and in particular to a method of scheduling the supply of cells mixing different classes of traffic, for example voice and data.
ATM is an asynchronous packet switching network in which data packets are broken into fixed-length cells of 53 bytes each and sent over virtual circuits established between a pair of communicating devices. The virtual circuits can be either permanent or switched, in which latter case the virtual circuit is set up by the network manager at the time of placing a "call" between the sending and receiving ends.
Although ATM is fundamentally asynchronous in its operation, one of the features offered by ATM is the ability to provide constant bit rate (CBR) services between the endpoints. CBR is important for time sensitive data, such as voice and video. CBR can be achieved by controlling the supply of cells into the network, buffering the cells at the receiving end and creating an output bit stream clocked by signals recovered from the ATM network using known clock recovery techniques.
It is often desired to mix variable bit rate (VBR) traffic with the CBR traffic in order to optimize the use of available bandwidth. VBR traffic consists of data that is not time sensitive, for example, computer files and the like or signaling information.
One of the problems that arises is in the scheduling of traffic into the ATM network. CBR traffic, which is delay sensitive must given priority over VBR traffic. Various approaches are known for controlling the supply of VBR and CBR cells. For example, VBR traffic can be sent out using the leaky bucket algorithm. For each virtual circuit, credits accumulate up to a pre-programmed maximum value at the average cell transmission rate. Each time a cell is sent, a credit is removed until the packets are segmented or no credits are left. As long as credits exist, cells are transmitted at the peak rate. CBR traffic is handled by a simple backpressure mechanism. When a CBR cell shows up at the interface, the controller stops the VBR (AAL5) assembly engine and lets the CBR cell through. This does not permit user control over the sending of CBR cells, and in particular is unsuitable for managing multiple CBR circuits, for example, from an ST-BUS backplane.
An object of the invention is to alleviate this problem.